1. Field of the Invention
The invention relates in general to a method of trench polishing, and more particularly, to a method of fabricating a shallow trench isolation (STI) by using a reverse active mask.
2. Description of the Related Art
The fabrication line width of semiconductor fabrication process is developed towards a wavelength shorter than 1 .mu.m as the design of integrated circuit becomes more and more complex. The very short line width limits the development of forming trench isolation in complementary metal-oxide semiconductor (CMOS). In the conventional technique of a planarization process by chemical mechanical polishing (CMP), if the underlying layer having a pattern with a pitch larger than 10 .mu.m, a dish-like recess is formed in the active region after planarization. The requirement of a global planarization thus can not be achieved. This is the so-called "dishing effect". FIG. 1A to FIG. 1D are cross sectional views showing a method of fabricating a shallow trench isolation by chemical mechanical polishing.
In FIG. 1A, a pad oxide layer 11 is formed on a substrate 10. A dielectric layer 12 is formed on the pad oxide layer 11. Using photolithography and etching process, the dielectric layer 12 is patterned to define a device region 13 covered by the patterned dielectric layer 12. The substrate 10 is then etched to form trenches as shown in the figure. In FIG. 1B, a silicon oxide layer 14 is formed over the substrate 10 to fill the trenches by chemical vapor deposition (CVD). By chemical mechanical polishing, the silicon oxide layer 14 is planarized with the dielectric layer 12 as a polishing stop, so that oxide plugs 15 and 16 are formed as shown in FIG. 1C. The dielectric layer on the active region 13 is then removed to form the shallow trench isolation structure.
It is known that the area of each isolation structure is not identical. As shown in FIG. 1C, the area of the shallow trench isolation 16 is much bigger than the area of the shallow trench isolation 15. The shallow trench isolation 16 with a larger area has a recessed surface after being polished. In FIG. 1D, while planarizing a polysilicon layer 18 formed on the substrate 10 subsequently, a global planarization thus cannot be achieved.
In the conventional method of fabricating a shallow trench isolation, a reverse diffusion layer mask and an etch back process for an oxide layer are used to achieve the uniformity of chemical mechanical polishing. However, as the line width is reached 0.25 .mu.m or even lower, the design rule is so tight that it is easy to cause misalignment during exposure. The problem of overlapping pattern occurs.